The invention relates to the general field of CMP (chemical mechanical polishing) with particular reference to elimination of differential polishing effects at the periphery of a wafer.
CMP (chemical mechanical polishing) has been a basic approach in planarization of sub-micron technology integrated circuits. A layer, such as an oxide layer, can be deposited over a pre-patterned conductive layer and can then be polished to a high degree of flatness which is important when dealing with very limited depths of focus during subsequent photolithographic processes.
The principal parts of a CMP apparatus are schematically illustrated in FIG. 1. Wafer 11 is mounted inside chuck 13 which includes a retaining ring 14. Polishing pad 12 is brought to bear against the upper surface of wafer 11 and the latter is kept pressed against it by means of elastic membrane 15. There is, however, always present a topography difference at the periphery of the wafer. This is exemplified by the raised areas 16 seen in the figure. For example, for a 200 mm wafer, the oxide surface in a peripheral region up to 20 mm wide, may end up about 1,000 xc3x85 above or below the central portion of the surface.
These topography differences that arise out of CMP are bad enough on an individual basis but they become particularly serious when they accumulate as a result of the deposition of multiple layers, each of which is planarized prior the deposition of the next layer. This has been illustrated in FIG. 2 which is for the case of a peripheral region 25 that ends up higher than the central region. Wafer 11 has been coated with 4 successive layers, 21, 22, 23, and 24 which cover patterned metal or polysilicon layers 26, 27, 28, and 29. Unlike FIG. 1, where polishing pad and retaining ring are shown as separate entities, both pad and retaining ring are shown here as a single entity 114 to simplify the presentation.
An example of a CMP apparatus in which the peripheral region 35 ends up lower than the central region is shown in FIG. 3. The principal difference between FIGS. 2 and 3 is that in the latter case the retaining ring included in 124 is of the slotted variety in which slots (symbolized as 36) are formed in said ring so as to allow for the easier removal of slurry during polishing. In this case, the peripheral effect is seen to grow steadily worse as successive layers 31, 32, 33, and 34 are laid down and then planarized.
In practice, whether the peripheral region ends up above or below the central region depends on a number of variables that are operative during CMP. This will be discussed in greater detail below as it is an understanding of these factors that have led to the solution of the peripheral height difference problem that comprises the present invention.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 6,051,499, Tolles et al. show a CMP tool and process with slotted carrier heads. Chang et al. disclose a planarization process in U.S. Pat No. 6,271,138 B1. U.S. Pat No. 5,899,745 (Kim et al.), and U.S. Pat No. 6,171,513 B1 (Davis et al.) are related CMP planarization processes.
It has been an object of at least one embodiment of the present invention to provide a process for planarizing a plurality of layers by means of CMP
Another object of at least one embodiment of the present invention has been that the last of said layers that are planarized emerge with a uniformly flat surface having little or no thickness differences between the periphery and the center.
Still another object of at least one embodiment of the present invention has been that said process utilize existing CMP equipment and be fully compatible with CMP processes currently in use as part of conventional manufacturing procedures.
These objects have been achieved by varying the type of polishing pad and retainer ring from one CMP operation to the next. Thus, if the equipment that is used to effect a given CMP step results in a post CMP surface in which the periphery of the wafer is higher that the center, CMP equipment for the next layer is selected that, operating alone, would result in a surface in which the periphery of the wafer is lower than the center, so the two CMP operations cancel each other and a uniformly flat final surface results. The conditions required to produce either surface topography are described and discussed.
FIG. 1 is a schematic representation of a standard CMP apparatus.
FIGS. 2 and 3 show how peripheral effects accumulate when successive layers are planarized and the same CMP equipment is used each time.
FIGS. 4-7 illustrate the process of the present invention wherein alternating layers are planarized using different CMP equipment for each.